1. Field of the Invention
The present invention relates to integrated circuits, and more particularly to integrated circuits having at least one metallization level and associated fabrication processes.
2. Description of Related Art
Conventional integrated circuits are surmounted by a plurality of interconnect layers comprising an alternation of conducting layers (also known as “metallization levels”) that are provided with metallized conducting lines extending parallel to the layer, and insulating layers that are penetrated by conducting vias for making electrical connections between two metallization levels.
A metallization level comprises a plurality of conducting lines surrounded by regions made of a dielectric. The local metal density due to the presence of the conducting lines may vary greatly within one and the same metallization level.
However, a low metal density in a localized region of a metallization level poses fabrication problems.
More specifically, when the conducting lines are based on aluminum, an aluminum layer is deposited on a dielectric layer. The aluminum layer is then etched in order to leave only the conducting lines. A layer of dielectric, for example silicon oxide, is then deposited in order to fill the empty spaces left between the conducting lines and to ensure their mutual isolation, and to form a dielectric layer above that metallization level.
A chemical-mechanical polishing (or CMP) step is then carried out in order to reduce the thickness and unevenness of the dielectric, and to obtain a planar surface so that the upper metallization levels can be properly formed. However, during deposition of the dielectric, the absence of metal in a localized area results in a hollow in the upper surface of the deposited dielectric layer, which hollow may be so large that the chemical-mechanical polishing is unable to make the surface of the dielectric layer even. As a result, a hollow remains, which seriously impairs the subsequent fabrication steps.
Similarly, if the conducting lines are made of copper, the positions of the future conducting lines are etched in a thick layer of dielectric and then filled with copper. This operation is then followed by chemical-mechanical polishing of the upper surface of the circuit being fabricated, so as to remove the excess copper and obtain a planar surface with which the conducting lines are flush.
If a localized area is devoid of copper, there is a risk, after the chemical-mechanical polishing, of an excess thickness of dielectric remaining, which the polishing was unable to remove. Again, this surface unevenness has serious drawbacks for the subsequent integrated circuit fabrication steps.
One known approach to solve this problem is to insert floating conductors, which are known as “dummy” conductors since they are of no electrical use, in the areas of low metal density of a metallization level. The entire metallization level then has a relatively uniform metal density, so as to optimize the efficiency of the fabrication processes. The dummy conductors are of greater importance the narrower the conducting lines become, so as to increase the interconnect density. However, the presence of such dummy conductors modifies the electrical characteristics of the interconnects around which they are placed, forming parasitic capacitances, with the risk of compromising the proper operation of the entire integrated circuit, and even more so as the conducting lines become narrower.
The technological evolution tending to increase the integration density, and therefore to reduce the width of the conducting lines, makes circuits more and more sensitive from the electrical standpoint to the presence of dummy conductors. Increasing the clock frequency of integrated circuits makes them more sensitive to parasitic capacitances, especially due to the longer propagation times that they cause.
The dummy conductors are generally in the form of square pads in the areas of low metal density of a metallization level. It would be conceivable to decrease the size of the dummy conductors so as to reduce the parasitic capacitances that they form with neighboring lines. However, the fabrication of a very large number of small dummy conductors has drawbacks in terms of circuit simplicity and fabrication yield. The presence of a very large number of small dummy conductors impedes post-fabrication analysis of defects, because of the screen formed which blocks the photon images and more generally the transmission of any type of photon, for example in HCMOS 9 technology. Thus, focused ion beam imaging, laser-induced circuit modification, infrared microscopy, observation by optical microscopy, laser marking, and so on may all be impeded by the presence of a very large number of small dummy conductors.